1. Field of the Invention
The present invention relates to a scheme for enhancement of power supply ripple rejection, and in particular, to a circuit for enhancing the power supply ripple rejection for operational amplifiers (op-amps) and low-dropout (LDO) voltage regulators.
2. Description of the Prior Art
Power Supply Rejection Ratio (PSRR), a measure of power-supply ripple rejection, is an important parameter for op-amps and op-amp based LDOs. With many types of circuits running off the same power supply line VDD, the DC voltage at VDD becomes corrupted with ripple voltage. The ripple voltage usually has a complex waveform having a frequency content from DC to several hundred kilohertz. For op-amp circuits to function properly, the op-amps concerned must be able to reject this unwanted ripple at the outputs up to as high frequency as possible. Alternatively, if an LDO regulator is used to clean-up this ripple, it must also be able to provide the same type of rejection. Ability to provide good rejection to power-supply ripple is indicated by a high PSRR figure (80 dB to 100 dB) for the circuit.
As it turns out, it is more convenient to work with the inverse of PSRR instead and this inverse will be referred to as the Power Supply Gain Ratio (PSGR). Thus, PSGR in dB=negative of PSRR in dB. Usually, the PSGR for an op-amp or LDO is good (typically −80 dB) at low frequencies: from DC to a few kilohertz. After that, the PSGR degrades with frequency at a rate of 20 dB/decade. Thus, the high frequency PSGR figures are poor. Please refer to FIG. 1. FIG. 1 is a frequency response diagram 10 showing PSGR figures for op-amps and LDOs with and without enhancement. The poor high frequency PSGR figures of the related art are shown by the solid line curve 12 in FIG. 1. Thus, the objective is to use enhancement in order to have better PSGR figures at higher frequencies as shown by the dashed line curve 14 in FIG. 1.
The most appropriate related art is authored by Mohamed El-Nozahi, Ahmed Amer, Joselyn Torres, Kamran Entesari and Edgar Sanchez-Sinencio, entitled “A 25 mA 0.13 μm CMOS LDO Regulator with Power-Supply Rejection Better Than −56 dB up to 10 MHz Using a Feedforward Ripple-Cancellation Technique,” and published in the ISSCC Digest of Technical Papers, pp. 330-331, on February 2009.
Please refer to FIG. 2. FIG. 2 shows a block-level representation of an LDO regulator 20 employing a feedforward cancellation technique according to the related art. The LDO regulator 20 utilizes a feedforward amplifier 22 together with a summing amplifier 24 for producing a cancellation path leading into the gate of a pass transistor MP. The output of error amplifier 26 is also input into the summing amplifier 24. Therefore, the technique described in the paper modifies the gate voltage of the pass transistor MP with power-supply ripple to achieve ripple cancellation at output VOUT for high frequencies. This related art circuit thus needs the LDO regulator 20 to be modified to include the summing amplifier 24 in order to perform addition of the error amplifier 26 output voltage with the power-supply ripple voltage to drive the gate of the pass transistor MP. However, considerable effort is required to redesign the circuit in order to employ the summing amplifier 24, which limits the appeal of the related art LDO regulator 20. In addition, the circuit redesign may be different for different circuits, requiring a custom redesign to be performed in many cases.